A conventional method used by the semiconductor industry in the manufacturing of semiconductor integrated circuits includes the steps of fabrication, wafer sort, assembly and test, respectively. As shown in FIG. 1, in the fabrication step, as many as several thousand dies (integrated circuits) 5 are formed onto a semiconductor wafer 4. In the wafer sort step, each of the dies 5 on the wafer 4 is tested to determine its electrical characteristics and operability, and defective dies are distinguished from operable dies. The defective dies are often marked by an ink mark at the wafer sorting step. In the assembly step, the unmarked, operable dies are assembled into a package, and in the test step, the packaged integrated circuits are tested for operability and reliability.
At the water sort step, the dies are tested to establish which dies on the wafer function properly. Each die is tested to all functional product specifications for both DC and AC parameters. Four testing objectives are pursued: (1) chip functionality, in which all chip functions are tested to ensure that only fully-functional chips are assembled and packaged in subsequent steps; (2) chip sorting, in which chips are separated or sorted on the basis of their operating speed performance under various voltage and timing conditions; (3) fab yield response, which yields important information that may lead to improvements in the overall fabrication process; and (4) test coverage, in which high test coverage of the internal device nodes is achieved at the lowest possible cost. The wafer sort procedure is similar to the in-line parametric test except that every die on the wafer is tested, in many cases using the same automated test equipment (ATE). Furthermore, the wafer sort procedure is usually located in a separate facility under less stringent purity conditions than those in which the parametric test is carried out, since wafer fabrication is essentially complete.
In automated wafer handling during wafer sort, a correlation wafer is used to verify tester setup. The correlation wafer is a control wafer the functionality of which has been verified and ensures that the testing system is working properly. After indexing from the cassette to the prober, the wafers are mounted on a vacuum chuck with Z (vertical) positioning. Using software, mechanical probe needles are aligned and contacted with bond pads on the wafer to establish electrical communication between the testing equipment and the dies on the wafer. The probes are interfaced with the ATE to perform the range of AC functional tests based on test algorithms. The type, number and order of tests are defined by the test program.
After testing, die found to be defective are labeled in a computer database to exclude the die from subsequent packaging steps. The labeling method is typically performed by placing a drop of ink on each unacceptable die. Because the ink marking process can be messy and introduce possible contaminants onto the chip, electronic wafer maps are increasingly being used to create a computer image of chip location and test results to categorize good and bad die on the wafer. At the chip assembly stations, the electronic water maps are downloaded into an equipment database to ensure that defective chips will not be packaged.
As further shown in FIG. 1, in an integrated circuit pattern of each dice 5, the input, output, power supply and other terminals of the circuit are formed by multiple metalized contact pads 6, adjacent ones of which are usually deployed in lines along the periphery or margins of the pattern in what is commonaly known in the art as a testkey pattern. Metal lines or traces 7 electrically connect the contact pads 6 to the circuit elements of the dice 5. The outline of the testkey pattern is either square or rectangular, and the marginal locations of the contact pads thereon depend on the circuit configuration and the available marginal space. Thus, in a relatively simple circuit pattern, all of the marginal space may be available for contact pads, whereas in more complex circuits, portions of the circuit may invade the marginal areas so that contact pad placement is restricted to the free marginal areas. In some instances, therefore, the contact pads may lie in more or less uniform rows along the margins, and in other cases, the contact pads may be randomly spaced from each other.
Immediately following manufacture of the IC, the electrical characteristics of the device must be tested using a test probe assembly which includes a test probe card consisting of a printed circuit board having an opening therein to provide access to an IC pattern. The opening is surrounded by a ring of conductive pads connected by the printed circuit card to terminals for connection to test equipment appropriate for testing the circuit. The number of pads in the ring determines the maximum capacity of the probe card.
During testing of IC devices, the wafer on which the devices are fabricated is supported on a wafer chuck. Typically, the probe needles on the probe card are inclined relative to the bonding pads on the integrated circuit devices. After the probe needles have been aligned with the bonding pads, the wafer chuck is raised through an “over-travel distance” of approximately 3 mils past the point at which the probe tips first contact the pads, such that the typically inclined probe needles slide or “scrub” on the bonding pads of the die to allow optimum mechanical and electrical contact between the probe needles and the bonding pads.
A higher degree of integration in recent semiconductor devices has led to an increase in the number of electrodes in ICs and to a decrease in the size of the electrode pads which are contacted by the probe needles. The reduction in size and increase in density of the probe needles has inevitably made the manufacture and mounting of the needles on the probe card troublesome. The tips of the probe needles are ideally all disposed at the same height level and same angle, but these and other parameters of the needles fluctuate somewhat for a number of reasons. These variations in probe needle parameters reduce test precision and reliability.
In the course of manufacturing a probe card, the probe needles on the card are aligned with dots or targets imprinted on a needle alignment mask. The locations of the dots or targets correspond precisely to the bonding pads on the die to be probed. As stated above, during testing of integrated circuit die, the probe needles are “overdriven” by approximately 3 mils. This renders it necessary to provide the same 3 mils of overdrive during alignment of the probe needles with the dots on the mask.
As shown in FIG. 2, probe needle alignment is typically carried out on an alignment station 10, in which a needle alignment mask 12 is placed on a vertically-movable chuck 14 with alignment dots 13 on the mask 12 facing upwardly. A probe card 16 having probe needles 18 to be aligned is mounted securely in the alignment station 10, with the probe needles 18 pointing downwardly and as closely-aligned as possible with the respective dots 13 on the mask 12. A skilled operator then manipulates tweezers (not shown) to adjust the alignment of the probe needles 18 with respect to the dots 13. To accomplish this task, the operator views the probe needles 18 through a microscope (not shown). When the chuck 14 is raised to provide the 3 mil overdrive, the operator identifies the needles 18 which require bending or adjustment to be properly aligned with the corresponding dots on the mask 12. The mask 12 is then lowered such that it no longer contacts the needles 18. The operator then manipulates the tweezers to bend the misaligned needles 18, again raises the chuck 14 to the overdrive position, and determines whether the adjusted needles 18 are properly aligned with their respective dots 13 on the mask 12. If not, then the needles 18 are again manipulated to align the needles 18 with the dots 13 on the mask 12. This procedure is repeated until all of the needles 18 are properly aligned with the corresponding dots 13 on the mask 12 in the overdriven position. At that point, the probe card 16 is ready for use in testing dies on a wafer.
One of the problems associated with the conventional alignment station 10 is that certain types of probe cards are not amenable to probe needle alignment on the station 10. These include multi-DUT (Die Under Test), stagger-type probe cards in which the probe needles are arranged in a staggered configuration for contact with multiple rows of contact pads on a wafer. Accordingly, an alignment station is needed which is suitable for testing probe needles on a variety of different types of probe cards and which is characterized by enhanced alignment efficiency.
An object of the present invention is to provide a new and improved alignment station for aligning probe needles on a probe card.
Another object of the present invention is to provide a new and improved alignment station which may be used to align probe needles on multi-DUT, stagger-type probe cards.
Still another object of the present invention is to provide a new and improved alignment station in which probe needles on a probe card extend upwardly and are contacted with dots on a mask to ascertain whether the probe needles on the probe card are properly aligned for testing devices on a wafer.
Yet another object of the present invention is to provide a new and improved alignment station which includes a probe card support for receiving a probe card and a mask carrier which supports a needle alignment mask and is operable to selectively lower the mask into contact with the probe needles to ascertain whether the probe needles are properly aligned and raise the mask out of contact with the probe needles to facilitate alignment adjustment of the probe needles, as needed.
A still further object of the present invention is to provide a new and improved alignment station which is characterized by enhanced alignment efficiency.
Yet another object of the present invention is to provide a new and improved alignment station for aligning probe needles on a probe card, which alignment station is capable of selectively moving probe needles on a probe card into contact with alignment dots on a needle alignment mask and moving the probe card away from the alignment mask to facilitate proper alignment of the probe needles for subsequent testing of integrated circuits on a wafer.